The exact design, version and block in scope
Internal Reference Projects
Our verification reference portfolio is in development
In development
We are building an internal portfolio of formal verification reference projects. Each project will be published here only once its work has been completed and reviewed.
- Completed
- Reviewed
- Published
PUBLICATION STANDARD
What each published project will show
Every project on this page will carry the material an experienced verification engineer needs to judge the work.
The verification plan and the properties written
The assumption register, with how each assumption was reviewed
Proof and cover results, including bounded or inconclusive ones
Bugs or issues found, and how they were resolved
The second engineer’s review
Internal work only
These are internal projects on in-house reference designs and selected open-source designs. They are not customer projects, and no customer design data is used in them. Where open-source designs are used, such as specified blocks of an open-source RISC-V core or SoC, the exact repository version and block scope will be stated. TeraSilicon IQ is independent and is not affiliated with, endorsed by or sponsored by the maintainers of those projects, and did not create the upstream designs.