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Formal Verification Insights
Practical notes from our formal engineers
Methodology, sign-off evidence and proof convergence, written for verification leads and for engineers learning formal.
Sign-offFive checks before trusting a green formal verification result
A green run is useful evidence, not sign-off. Check the properties, assumptions, vacuity, proof depth and counterexamples first.
Methodology and timingUnverified SDC exceptions: why formal should check their functional assumptions
Formal can check selected functional conditions behind a timing exception. STA still has to check the constraint itself.
Equivalence and sign-offThe late-stage ECO trap: why LEC and formal property verification need each other
Equivalence checking shows the netlist matches the RTL. It does not show the RTL change itself is correct.
MethodologyOver-constraint: how one assumption can hide a real bug
Assumptions make formal tractable. A single wrong one can make a proof pass on a broken design.
Front-end to implementationOne set of constraints: closing the gap between formal sign-off and timing sign-off
Formal and STA use different models, but both depend on the same clocks, resets and modes. Review them together.
Proof convergenceBounded proofs: when is depth K enough?
No counterexample up to depth K is not the same as a full proof. The bound has to fit the design and the property.
ProductivityReusable property libraries: why writing SVA from scratch wastes schedule
Common interfaces follow the same rules on every project. Reuse reviewed verification intent, not just code.
InterconnectWhy deadlock bugs can escape simulation
Progress failures hide in sequences a testbench never runs. Formal can check them, if progress and fairness are defined correctly.
Buyer’s guideOutsourcing ASIC sign-off: ten questions to ask before sharing RTL
Agree scope, deliverables, reporting and confidentiality before any RTL leaves your team.